1. Technical Field
The present invention relates to a method for manufacturing a semiconductor device and to a semiconductor device.
2. Description of the Related Art
Semiconductor integrated circuits, particularly integrated circuits using MOS transistors, are increasing in integration. With increases in integration, MOS transistors used in the integrated circuits are increasingly made finer up to a nano region. Finer MOS transistors have the problem of difficulty in suppressing leak currents and difficulty in decreasing the areas occupied by circuits because of the demand for securing necessary amounts of currents. In order to resolve the problem, there have been proposed surrounding gate transistors (SGT) having a structure in which a source, a gate, and a drain are disposed in a direction vertical to a substrate, and the gate surrounds a pillar-shaped semiconductor layer (for example, Japanese Unexamined Patent Application Publication Nos. 2-71556, 2-188966, and 3-145761).
By using a metal for a gate electrode instead of using polysilicon, depletion can be suppressed, and the resistance of the gate electrode can be decreased. However, a manufacturing process after a metal gate is formed must be one in which metal contamination by the metal gate is always taken into consideration.
In addition, in order to satisfy both a metal gate process and a high-temperature process for usual MOS transistors, a metal gate last process is used for actual products, in which a metal gate is formed after a high-temperature process (IEDM 2007 K. Mistry, et. al., pp. 247-250). The gate is formed using polysilicon, and then an interlayer insulating film is deposited. Then, the polysilicon gate is exposed by chemical mechanical polishing and etched, followed by deposition of a metal. Therefore, in order to satisfy both the metal gate process and the high-temperature process, the metal gate last process must be used for SGT, in which a metal gate is formed after the high-temperature process. Since, in the SGT, the top position of the pillar-shaped silicon layer is higher than the gate, some consideration is required for using the metal gate last process.
In addition, usual MOS transistors use a first insulating film in order to decrease a parasitic capacitance between gate line and a substrate. For example, in FINFET (IEDM 2010 CC. Wu, et. al., 27.1.1-27.1.4.), a first insulating film is formed around a fin-shaped semiconductor layer and then etched back to expose the fin-shaped semiconductor layer, thereby decreasing the parasitic capacitance between the gate line and the substrate. Also, in SGT, the first insulating film must be used for decreasing the parasitic capacitance between the gate line and the substrate. The SGT includes the pillar-shaped semiconductor layer in addition to the fin-shaped semiconductor layer, and thus some consideration is required for forming the pillar-shaped semiconductor layer.
On the other hand, FIN FET has been known, in which two transistors are formed from one dummy pattern (for example, Japanese Unexamined Patent Application Publication No. 2011-71235). A sidewall is formed around the dummy pattern and used as a mask for etching a substrate to form a fin, thereby forming two transistors from one dummy pattern.
Since the two transistors are formed, one of the transistors can be used as an nMOS transistor and the other one can be used a pMOS transistor.